Memory devices are well known in the art and used in, among other things, virtually all microprocessor and digital signal processor (DSP) applications. One type of memory favored for many applications is Static Random Access Memory (SRAM). SRAM devices are fast and easy to use relative to many other types of memory devices. In addition, SRAM devices using metal-oxide-semiconductor (MOS) technology exhibit relatively low standby power and do not require a refresh cycle to maintain stored information. These attributes make SRAM devices particularly desirable for battery-powered equipment, such as laptop computers and personal digital assistants.
Miniaturization of SRAM devices is another attribute that may make SRAM devices desirable for such battery-powered equipment. Desired miniaturization, however, may include undesirable operating problems for the smaller SRAM devices. For example, current leakage may increase as the size of SRAM devices decreases. Current leakage may provide a problem during a sleep mode, a standby mode and even during an active mode. In fact, current leakage, which may be represented by IDDQ, has become a greater concern during the active mode as SRAM devices continue to decrease in size.
Some options to reduce current leakage during the active mode already exists. In one such option, for example, the high operating voltage, VDD, supplied to the SRAM device may be reduced to lower the voltage across the SRAM array. A reduced high operating voltage VDD, however, can also reduce static noise margin (SNM) and write trip voltage (so-called “Vtrip”) below acceptable levels. Alternatively, a low operating voltage, VSS, supplied to the SRAM device can be raised while in a standby mode and lowered when in the active mode. This alternative, unfortunately, requires more switching power and does not support the write trip voltage Vtrip.
A high Vtrip and SNM are desired cell characteristics of SRAM devices. A high SNM is desired for circuit stability. If SNM is too low, READ operations may be disrupted. A high Vtrip is desired for adequate data write speed. If Vtrip is too low, WRITE operations may be disrupted. Unfortunately, the requirements for an acceptable SNM and write trip voltage Vtrip may limit the tolerances for an acceptable SRAM yield during manufacturing since increasing one typically decreases the other.
A typical six-transistor SRAM memory cell (the basic unit of a SRAM device) consists of two p-channel “pull-up” transistors, two n-channel “pull-down” transistors and two access transistors, which are typically n-channel transistors. The strength of the p-doped and n-doped channels of the transistors affects the performance of the SRAM memory cell as a whole. For example, a strong n-channel can cause SNM to be unsuitably low, particularly when accompanied by a weak p-channel. One might be tempted to weaken the n-channel and/or strengthen the p-channel to achieve a satisfactory SNM. However, a weak n-channel can cause Vtrip to be unsuitably low, particularly when accompanied by a strong p-channel.
Thus, existing SRAM devices are challenged by the competing and contradicting objectives of providing a weak n-channel (and/or a strong p-channel) to achieve an acceptable SNM and providing a strong n-channel (and/or a weak p-channel) to achieve an acceptable Vtrip. Moreover, this trade-off between SNM and Vtrip (and, thus, between reliable READ and WRITE operations) becomes increasingly constrained with continued miniaturization and lower operating voltages since these amplify the effect of normal manufacturing variations.
Even though both SNM and Vtrip are degraded when the high operating voltage VDD is reduced, a reduction of the high operating voltage VDD is often desirable for low power operation and for some test conditions. Though both SNM and Vtrip are degraded, the degradation of Vtrip is particularly strong with a reduction in the high operating voltage VDD. Thus Vtrip tends to limit the lower bound of the high operating voltage VDD for operation. A solution for reducing current leakage during an active mode, therefore, needs to provide a minimum adverse affect on SNM and Vtrip.
Accordingly, what is needed in the art is an improved SRAM device having reduced current leakage during an active mode. Additionally, the improved SRAM device with reduced current leakage needs a strong SNM and write trip voltage Vtrip.